Parallelized Booth-Encoded Radix-4 Montgomery Multipliers

This paper proposes two parallelized radix-4 scalable Montgomery multiplier implementations. The designs do not require precomputed hard multiples of the operands, but instead uses Booth encoding to compute products. The designs use a novel method for propagating the sign bits for negative partial products. The first design right shifts operands to reduce critical path length when using Booth encoding. The second design left shifts operands to improve latency between processing elements and to decrease hardware usage. An FPGA implementation of the right-shifting design consumes 17% more lookup tables (LUTs) and 25% to 33% more flip-flops than a comparable non-Booth encoded design. It performs 1024-bit modular exponentiation in 9.1 ms using 5959 LUTs and 5079 flipflops. The left-shifting design consumes 3% fewer LUTs and 29% to 33% fewer REGs than non-Booth. Its clock speed is 25% slower than non-Booth, and it performs 1024-bit modular exponentiation in 13 ms using 4852 LUTs and 2887 flip-flops.